A. Field of the Invention
The present invention relates to a semiconductor device and semiconductor device manufacturing method.
B. Description of the Related Art
A reverse blocking type of semiconductor element having bidirectional voltage resistance characteristics is commonly known as a power semiconductor element used in a power converting device or the like. With the reverse blocking type of semiconductor element, it is necessary to extend a p-n junction from the rear surface to the front surface of the semiconductor element in order to ensure reverse voltage resistance. In order to form the p-n junction extending from the rear surface to the front surface, a separation layer formed from a diffusion layer is provided in an element end portion of the semiconductor element.
A reverse blocking type of semiconductor element in which a depression portion is provided in the rear surface of an element end portion, including a portion (hereafter called an eave portion) thinner than an active region side is commonly known. In this case, the separation layer is provided in the eave portion, which is the element end portion. In order to form the p-n junction extending from the rear surface to the front surface the p-n junction is also provided on a side wall and bottom surface of the depressed portion.
As this kind of reverse blocking type of semiconductor element, in a semiconductor device including a first conductivity type semiconductor substrate, a second conductivity type first region formed in a peripheral portion of a surface layer of a first main surface of the semiconductor substrate, a second conductivity type well region formed on a surface layer of the first main surface of the semiconductor substrate, detached from the first region and surrounded by the first region, a first conductivity type emitter region formed on a surface layer of the well region, a gate electrode, sandwiched between the emitter region and semiconductor substrate, formed across a gate insulating film on the well region, an interlayer insulating film whose surface is covered, including on the gate electrode, an emitter electrode in contact with the emitter region and well region formed on the interlayer insulating film, a passivation film formed on the emitter electrode, on the first region, and on the semiconductor substrate, a collector layer formed on a surface layer of a second main surface of the semiconductor substrate, a second conductivity type separation layer in contact with the first main surface and second main surface formed on a surface layer of a side wall of the semiconductor substrate in such a way as to make contact with the first region and collector layer, and a collector electrode on the collector layer, there is proposed an element formed from a first side wall wherein the side wall of the semiconductor substrate makes contact vertically with the first main surface, and makes contact with the first region, and a second side wall connected to the first side wall and second main surface, wherein the angle formed with the first side wall is 90 degrees or more (for example, refer to International Publication No. 2009/139417, pamphlet).
As a reverse blocking type of semiconductor element wherein, by a depressed portion passing from the rear surface through to the front surface of the semiconductor element being provided, no eave portion is provided, there is proposed an element including a second conductivity type base region selectively provided in a surface region of a first main surface of a first conductivity type semiconductor substrate, a first conductivity type emitter region selectively provided in a surface region of the base region, an MOS gate structure including a gate insulating film formed on a portion of the surface of the base region sandwiched by the semiconductor substrate and emitter region and a gate electrode provided on the gate insulating film, an emitter electrode in contact with the emitter region and base region, a second conductivity type collector layer provided on a surface layer of a second main surface of the semiconductor substrate, a collector electrode in contact with the collector layer, and a second conductivity type separation layer linked to the collector layer, surrounding the MOS gate structure, and reaching the first main surface from the second main surface at an inclination with respect to the first main surface, wherein the separation layer is covered with the collector electrode (for example, refer to JP-A-2006-303410).
As a semiconductor element whose element end portion is thin in comparison with an active region side, there is proposed an element in which a first semiconductor region on a base layer of a semiconductor substrate is formed from a semiconductor layer of the same conductivity type as the base layer, a second semiconductor region p-n joined to the first semiconductor region is formed from a semiconductor layer of a conductivity type differing from that of the first semiconductor region, a mesa portion forming an inclined surface is formed in an outer peripheral edge portion of the semiconductor substrate, a protective film is formed covering the inclined surface of the mesa portion, the second semiconductor region is formed divided evenly into a main region in contact with a first electrode and a sub-region not in contact with the first electrode, and one portion of the first semiconductor region is interposed between the main region and sub-region of the second semiconductor region (for example, refer to JP-A-2008-130622).
The following method is proposed as a manufacturing method of a reverse blocking type of semiconductor element. A thin semiconductor wafer on which are formed a front surface structure and rear surface structure configuring a semiconductor chip is affixed to a support substrate with two-sided adhesive tape, a trench, which is to be a scribe line, is formed with the crystal face exposed in the thin semiconductor wafer by a wet anisotropic etching, and a separation layer that maintains reverse voltage resistance is formed by an ion implantation and low temperature annealing or laser annealing in a side surface of the trench with the crystal face exposed in such a way as to extend to the front surface side in contact with a p-collector region, which is a rear surface diffusion layer. After carrying out a laser dicing, cleanly cutting the collector electrode by an appropriate amount below the separation layer, the two-sided adhesive tape is removed from the collector electrode, obtaining a semiconductor chip (for example, refer to JP-A-2006-303410 and JP-A-2006-156926).
An alternative method has been proposed. A surface element is formed on a surface of a semiconductor wafer, with the surface on which the surface element is formed facing up. Then, an etching mask is formed using a double-sided aligner. Next, a support substrate is joined to the surface element side, and a trench is formed by etching. Continuing, the etching mask is removed, and a metal film is formed. At this time, for example, an electrode protecting mask is formed above the trench so that the metal film is not formed on a side surface of the semiconductor wafer or in the trench. Then, the support substrate is detached, and chips are obtained by dicing (for example, refer to JP-A-2007-123357).
Also, there is proposed a power device having a package structure in which a semiconductor chip on which is formed the heretofore described reverse blocking type of semiconductor element is joined onto an insulating substrate by the same method as for a flat semiconductor chip. FIG. 36 is a sectional view showing a main portion of a structure of a heretofore known semiconductor device. The semiconductor device shown in FIG. 36 includes semiconductor chip 100, and insulating substrate 112 such as a ceramic insulating substrate (a DBC substrate: a direct bonding copper substrate). In FIG. 36, in order to clarify the junction portion between insulating substrate 112 and semiconductor chip 100, a resin case, an external terminal, a wire bonding, and the like, are omitted from the drawing (the same also applies hereafter in FIGS. 1, 10, 13, 18, and 35).
The heretofore described kind of reverse blocking type of semiconductor element is formed on semiconductor chip 100. Specifically, front surface element structure 102 such as an MOS gate structure or voltage resistant structure is provided on the front surface of n-type drift region 101 formed from semiconductor chip 100. A base region, an emitter region, and the like, provided on a surface layer of drift region 101 are omitted from the drawing (the same also applies hereafter in FIGS. 1 to 20, 37, and 38). P-type separation layer 103 is provided on a side surface of an element end portion of semiconductor chip 100.
By depressed portion 104 reaching separation layer 103 being provided in the element end portion on the rear surface of semiconductor chip 100, eave portion 105 is formed. Also, p-type collector layer 106 is provided on the surface layer of drift region 101, as a rear surface element structure, on the rear surface of semiconductor chip 100. Collector layer 106 extends to a side wall and bottom surface of depressed portion 104, and is connected to separation layer 103. Collector electrode 107 is provided over the whole surface of collector layer 106.
Collector electrode 107 provided over the whole of the rear surface of semiconductor chip 100 is joined via solder layer 111 to a circuit pattern (hereafter called a Cu pattern) formed from copper (Cu) or the like on insulating substrate 112. That is, solder layer 111 is formed more thickly in a region under eave portion 105 than on the active region side. Then, the whole of the rear surface of semiconductor chip 100 is joined to the Cu pattern of insulating substrate 112 (hereafter called simply insulating substrate 112) via solder layer 111. Although omitted from the drawing, the surface of insulating substrate 112 opposite to the surface on which the Cu pattern is provided is joined by soldering to, for example, a Cu base for cooling.
FIGS. 37 and 38 are illustrations sequentially showing a heretofore known semiconductor device manufacturing method. Herein, although the semiconductor wafer is shown in the drawing with the front surface facing up, the surfaces of the semiconductor wafer are inverted as appropriate in each step (the same also applies hereafter in FIGS. 2 to 9, 11, 12, 14 to 17, 19, and 20). Firstly, as shown in FIG. 37, separation layer 103 formed from a p-type diffusion layer, and front surface element structure 102 such as an MOS gate structure or voltage resistant structure, are formed sequentially on the front surface of n-type semiconductor wafer 201.
Next, depressed portion 104 reaching the separation layer 103, and collector layer 106 extending to the side wall and bottom surface of depressed portion 104 and connected to separation layer 103, are formed on the rear surface of semiconductor wafer 201. Depressed portion 104 is formed on, for example, the scribe line of semiconductor wafer 201. Next, collector electrode 107, in contact with collector layer 106 and extending to the side wall and bottom surface of depressed portion 104, is formed.
Next, as shown in FIG. 38, dicing tape 204 is affixed to the rear surface of the semiconductor wafer, and the semiconductor wafer is placed on, for example, a flat stand. Then, the semiconductor wafer is diced along the scribe lines, and the semiconductor wafer is cut into individual semiconductor chips 100. Next, by joining semiconductor chip 100 to insulating substrate 112 via solder layer 111, the semiconductor device shown in FIG. 36 is completed.
In this way, as a semiconductor device having a package structure wherein a semiconductor chip is joined via a solder layer to an insulating substrate, there is proposed a device including a mounting part, having on a lower surface inner side a solder attachment surface having solder wettability that is smaller than the external dimensions of the mounting part, formed in such a way that the solder attachment surface protrudes below an outer side surface of the mounting part, a mounted body, whose perimeter is surrounded by a solder resist that does not have solder wettability, that has a solder resist opening portion having solder wettability on which the solder attachment surface of the mounting part is placed, and a solder that joins the solder attachment surface of the mounting part and the solder resist opening portion of the mounted body, wherein the solder resist opening portion of the mounted body is surrounded by the solder resist in such a way that a narrow portion slightly larger than the dimensions of the solder attachment surface of the mounting part, and a wide portion larger than the external dimensions of the mounting part, are adjacent on each edge (for example, refer to JP-A-2006-049777).
However, in the semiconductor device shown in FIG. 36, each member, such as semiconductor chip 100, insulating substrate 112, the Cu pattern (not shown) on insulating substrate 112, and the Cu base (not shown), has a different thermal expansion rate. Furthermore, eave portion 105, which is thinner than the active region side, is provided in the element end portion of semiconductor chip 100. Then, eave portion 105 is completely joined to insulating substrate 112 via solder layer 111.
When a thermal shock such as thermal stress is applied to this kind of semiconductor device using, for example, a temperature cycle (H/C), each of the members configuring the semiconductor device expands at a different thermal expansion rate. For this reason, stress due to the expansion of the other members is exerted from the exterior on semiconductor chip 100, which is completely joined to the other members, and a bending stress is exerted on eave portion 105, which is thinner than the active region side. Because of this, the following problems occur in the element end portion of semiconductor chip 100.
FIG. 35 is a sectional view showing in detail a main portion of a structure of a heretofore known semiconductor device. As shown in FIG. 35, p+ field limiting ring (FLR) 121, field plate (FP) 122, passivation film 123, and the like, are provided as, for example, a voltage resistant structure in an element end portion of semiconductor chip 100. When bending stress is exerted on eave portion 105 as heretofore described, crack 131 occurs at the base of eave portion 105, that is, at the boundary between eave portion 105 and a portion of semiconductor chip 100 thicker than eave portion 105. Because of this, there is a danger of breakage or chipping occurring in semiconductor chip 100. Also, crack 132 and detachment 133 occur in FP 122 and passivation film 123 provided on eave portion 105. Because of this, there occurs a danger of the device characteristics of the semiconductor device deteriorating.
Also, in an inner portion of FP 122 formed from, for example, an aluminum (Al) alloy, an intermetallic compound formed from a constituent of the Al alloy grows due to a thermal shock such as thermal stress applied to the semiconductor device, and a void occurs due to the growth of the intermetallic compound. Because of this, there is a danger of the device characteristics of the semiconductor device deteriorating. Furthermore, due to the stress exerted on eave portion 105 of the semiconductor chip, the void in the inner portion of FP 122 provided on eave portion 105 changes shape, and there is a danger of cracking or detachment occurring in FP 122 or in the passivation film 123 in contact with FP 122.
The heretofore described problems, not being limited to the semiconductor device shown in FIG. 35, occur in the same way in the semiconductor device shown in JP-A-2006-303410 in which is mounted a semiconductor chip in which no eave portion is provided. For example, with the semiconductor device shown in JP-A-2006-303410, a cracking or detachment occurs in a passivation film provided on the front surface of the semiconductor chip.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.